1. Technical Field
The present disclosure is directed to a method and system for determining a dummy structure fill pattern to minimize erosion and dishing during chemical mechanical polishing, and more particularly, to a method for spacing dummy structures in accordance with the golden ratio.
2. Description of the Related Art
Chemical mechanical polishing (CMP) is a planarization process used in semiconductor manufacturing to form uniform surfaces at various levels on a wafer. A semiconductor wafer has various levels of metal conductors with insulators in between each metal layer.
FIGS. 1-3 are cross-sectional views of a known process of forming first and second metal structures 10, 12 in trenches 13 in a dielectric layer 14 at one of the metal levels. The first metal structure 10 is a metal interconnect that is used in the circuitry and the second metal structure 12 is a dummy structure, which is not used for circuitry but is used to assist in planarization. The dielectric layer 14 has been patterned to form trenches 13 to define the metal structures 10, 12 in the process of manufacturing the wafer.
A barrier layer 16 is formed on the dielectric layer 14 to protect the dielectric layer 14 from a copper layer 18. The barrier layer 14 may be tantalum or tantalum nitride. A copper plating or deposition process forms excess copper structures that have irregular or non-uniform features 20 across the top surface of the die. The various copper deposition processes form different non-uniform features 20.
Manufacturers use CMP to remove these non-uniform features 20 and the excess portions of the copper layer 18 to form the metal structures 10, 12. CMP takes advantage of cooperative effects of both physical and chemical forces acting on the surface of the wafer. Both the wafer and the pad counter rotate to remove the non-uniform features 20 as an abrasive chemical solution, called a slurry, passes between the pad and the wafer. Hydrogen peroxide is often used as the slurry to remove copper, because hydrogen peroxide reacts with the copper form a soft layer that increases the removal rate and aids in removing the non-uniform features 20.
CMP polishes sequentially or simultaneously portions of all three materials, the copper layer 18, the barrier layer 16, and the dielectric 14. FIG. 2 is an intermediate step in the CMP process where the excess portions of the copper layer 18 and the barrier layer 16 have been removed before any of the dielectric layer 14 has been removed. Some CMP processes will stop on the barrier layer 16 and switch to a different slurry. For example, since tantalum has different polishing properties than copper it may be desirable to change slurries and possibly a different pad to obtain a high selectivity between the barrier and copper. If the copper thickness is not uniform, the barrier layer 16 is exposed for longer periods of time where the copper is thinner as the thicker areas of copper are polished. Overpolish refers to the time from when the barrier layer 16 is first exposed and when the last of the thicker area of copper layer 18 is removed.
In FIG. 2, a first top surface 22 of the dielectric layer 14 and the metal structures 10, 12 are exposed by the CMP. After the dielectric layer 14 is first exposed, in some circumstances, the polishing process continues in an overetch to remove all the copper residue and strippers. This will also cause removal of the top portion. of the dielectric layer 14. This dielectric removal addresses underlying topography problems remaining from previous CMP steps and other irregularities in the first top surface 22.
The dielectric layer 14 may be an ultra low-k dielectric of the type normally used between metal layers. Ultra low-k dielectrics are used as interlayer dielectrics because of their low dielectric constants and their ability to reduce the capacitance of metal interconnects. However, ultra low-k dielectrics have air gaps in the material that can cause the ultra low-k dielectrics to degrade more quickly during CMP.
In order to remove the portions of the dielectric layer 14, a different slurry is selected. The slurry depends on both a hardness of the material to be removed and the chemistry of the slurry.
FIG. 3 is the cross-sectional view of the metal structures 10, 12 after the portions of the dielectric layer 14 have been removed. A second top surface 24 of the dielectric layer 14 is exposed. As the dielectric layer 14 is removed, the copper in the metal structures 10, 12 is also removed. Dishing causes the copper in the metal structure 10 to be lower than the second top surface 24 by a first distance 26. Dishing is a result of accelerated polishing at a center of a large metal structure, such as the first metal interconnect 10. Dishing is more prevalent at the global wiring level of the die. The dielectric layer 14 acts as a stop for the pad of the CMP, however, the pad elastically deforms with the back pressure and removes portions of the larger metal interconnects 10.
Erosion is another potential problem during CMP when there is an insufficient amount of the dielectric layer 14 to act as a CMP stop. This can occur where there is a high density of metal structures with small amounts of dielectric between each metal structure, for example, in dense sub-micron copper regions of a die. As in FIG. 3, erosion causes the copper in the metal structures 12 to be lower than the second top surface 24 by a second distance 28. These dishing and erosion issues can occur at the poly level or at the various metal levels. In addition, dishing and erosion are more significant at the edges of the die because these die polish faster.
CMP provides a more uniform planarization when the metal structures 10, 12 are evenly distributed across the wafer. In other words, CMP performs best when there is a uniform density of the metal structures 10, 12. However, the density and size of the metal structures 10, 12 vary at each metal level. In places where no metal structures 10, 12 are formed, unfilled portions of the dielectric layer 14 remain. These unfilled portions are filled with dummy structures to achieve a more uniform density of metal or poly for each metal or poly level, i.e., areas of each die that have low density of metal feature filled with dummy structures. The dummy structures are formed simultaneously with the metal structures 10, 12, such as with a single mask that includes mask features for both the metal structures and the dummy structures.
When these unfilled portions are not filed with dummy structures, the uneven distribution of the metal structures 10, 12 can cause dishing and erosion. The dishing and erosion can cause metal interconnects to not operate correctly by shorting the interconnect. However, determining the optimal arrangement and density of dummy structures is difficult.